FAST SEQUENTIAL INTEGER RADIX-4 DIVIDER
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One-clock divisor and dividend normalization unit, which occupies slightly more area compared to the sequential (multi cycle) normalization units is designed. A novel method to determine the overflow situation in signed and unsigned integer division, which minimizes the hardware resources footprint and reduces their energy consumption, is proposed. The various architectural options for pipelining the integer radix-4 divider, using the designed one-clock normalization unit and proposed overflow detection method, are compared.