DOI: 10.17586/2226-1494-2018-18-2-339-345


INTEGRATED CIRCUITS TIMING ANALYSIS WITH ACCOUNT OF PAD MODELS AND BOND WIRES

N. N. Nevirkovets , N. M. Chernetskaya, D. V. Kostygov, Y. V. Belyaev


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For citation: Nevirkovets N.N., Chernetskaya N.M., Kostygov D.V., Belyaev Ya.V. Integrated circuits timing analysis with account of pad models and bond wires. Scientific and Technical Journal of Information Technologies, Mechanics and Optics, 2018, vol. 18, no. 2, pp. 339–345 (in Russian). doi: 10.17586/2226-1494-2018-18-2-339-345

Abstract

Subject of Research.Timing analysis is an important stage in the design of integrated circuits. It makes possible to detect various types of errors, related both to the structure of blocks and to the violation of temporal characteristics at all levels of abstraction. It is especially important to detect errors in the interface blocks of the integrated circuit, since, otherwise, the final device may not meet the requirements of dynamic characteristics. Method. A technique for timing analysis of the integrated circuit is proposed considering the models of the contact pads and package bond wires, designed for taking into account the effect of the parameters of contact pads, bond wires, and external analog components. The technique is an extension of the standard IC verification flow with the addition of stages for analyzing and modeling of the contact pad parameters and bond wires. Main Results. The technique was used to verify the I2C interface block according to 350 nm technology. The I2C interface was included in the integrated circuit of a micromechanical accelerometer. The technique gives the possibility for detecting of errors that were not revealed during the integrated circuit design in accordance with the traditional design flow. The dynamic characteristics of the I2C controller were determined when connecting the SCK and SDA buses to the supply voltage through a resistor of 10 kΩ. Practical Relevance. The proposed technique can be used in the design of integrated circuit interface blocks. The technique takes into account the effect of the parameters of the contact pads and package of the integrated circuit, bond wires and external components on the dynamic characteristics of the circuit. It is advisable to use the technique for critical blocks, in particular, interface ones, the inoperability of which can lead to the impossibility of exchanging IC data with the consumer and, as a result, high financial costs for a new stage of IC design.


Keywords: micromechanical accelerometer, integrated circuits, digital integrated circuits, timing analysis, register-transfer model

Acknowledgements. This work was supported by the project no. 16-08-00640 of the Russian Foundation for Basic Research, the Russian Federation.

References
 
  1. Stempkovskii A.L., Gavrilov S.V., Glebov A.L. Methods of Logical and Logic-Time Analysis of Digital CMOS VLSI. Moscow, Nauka Publ., 2007, 220 p. (in Russian)
  2. Amon T., Borriello G. An approach to symbolic timing verification. Proc. 29th ACM/IEEE Design Automation Conference. Anaheim, USA, 1992, pp. 410–413.
  3. Gladstone B. Accurate timing analysis holds the key to performance in today’s system designs. EDA, 1993.
  4. Solov'ev R.A., Glebov A.L., Gavrilov S.V. Static time analysis with detection of false conductive paths based on logical implication. Proc. Problems of Advanced Micro- and Nanoelectronic Systems Development, 2006, pp. 22–28. (in Russian)
  5. Knyazev N.A., Malinauskas K.K. Critical path search algorithms for static timing analysis of digital. Information Technology, 2012, no. 11, pp. 2–9. (in Russian)
  6. Kaesli H. Digital Integrated Circuit Design: from VLSI Architectures to CMOS Fabrication. Cambridge University, 2008, 866 p.
  7. Allan G. Digital IC Design Flow. Royal Military College of Canada, 2008.
  8. de Graaf A.C., van Leuken T.G.R. Digital Design Flow. Delft University of Technology, Switzerland, 2006.
  9. Vachoux A. Top-Down Digital Design Flow. EPFL, Lausanne,Switzerland, 2011.
  10. Anikina A.A., Kostygov D.V., Nevirkovets N.N. The route of designing of digital blocks for specialized integrated circuits in Cadence. Proc. 69th Scientific and Technical Conference of the Faculty Members SPbSETU LETI. St. Petersburg, 2016, pp. 121–126. (in Russian)
  11. Tsai T.-Y., Chen S.-H., Chen Y.-F. A precise timing budgeting flow for SiP co-design. Proc. Design Automation Conference, 2010.
  12. Lee Y.-J., Lim S.K. Timing analysis and optimization for many-tier 3D ICs. Proc. IEEE International 3D System Integration Conference, 2010.
  13. Rabaey J.M., Chandrakasan A., Nicolic B. Digital Integrated Circuits. A Design Perspective. 2nd ed. Prentice Hall,2003, 761 p.
  14. CMOS Processes 0.35µm. Available at: http://ams.com/eng/Products/Full-Service-Foundry/Process-Technology/CMOS (accessed: 02.03.2018).
  15. Overhauser D. Fast Timing Simulation of MOS VLSI Circuits. PhD thesis. University of Illinois, 1989.
  16. Dharchoudhury A., Kang S.M., Kim K.H., Lee S.H. Fast and accurate timing simulation with region wise quadratic models of MOS I-V characteristics. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994, pp. 190–194.


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