Keywords: CAD, EDA, VLSI, optimization of combinational schemes, Boolean networks, partially defined Boolean functions, implicit Don’t Cares, ODC, relational theory, relational algebra, natural join
References
1. De Micheli G. Synchronous logic synthesis: algorithms for cycle-time minimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991, vol. 10, no. 1, pp. 63–73. doi: 10.1109/43.62792
2. Hachtel G.D., Rho J.K., Somenzi F., Jacoby R. Exact and heuristic algorithms for the minimization of incompletely specified state machines. Proc. of European Conference on Design Automation. Amsterdam, Netherlands, 1992, pp. 184–191.
3. Bogatyrev V.A., Bogatyrev S.V., Golubev I.Yu. Optimization and the process of task distribution between computer system clusters. Automatic Control and Computer Sciences, 2012, vol. 46, no. 3, pp. 103–111. doi: 10.3103/S0146411612030029
4. Sentovich E.M., Singh K.J., Lavagno L., Moon C., Murgai R., Saldanha A., Savoj H., Stephan P.R., Brayton R.K., Sangiovanni-Vincentelli A.L. SIS: a System for Sequential Circuit Synthesis. Technical Report UCB/ERL M92/41, Electronics Research Lab, Univ. of California, Berkeley, 1992.
5. Pederson D.O. The VIS Group. VIS: Verification Interacting with Synthesis, 1995. Available at: http://embedded.eecs.berkeley.edu/Respep/Research/vis (accessed 04.12.2013).
6. Bartlett K.A., Brayton R.K., Hachtel G.D., Jacoby R.M., Morrison C.R., Rudell R.L., Sangiovanni-Vincentelli A., Wang A. Multi-level logic minimization using implicit don’t cares. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988, vol. 7, no. 6, pp. 723–740. doi: 10.1109/43.3211
7. Fujiwara H. Logic Testing and Design for Testability. Cambridge: MIT Press, 1985, 304 p.
8. Chang A.C.L., Reed I.S., Beans A.V. Path sensitization, partial boolean difference and automated fault diagnosis. IEEE Transactions on Computers, 1972, vol. C-21, no. 2, pp. 189–195.
9. Bogatyrev V.A. Exchange of duplicated computing complexes in fault-tolerant systems. Automatic Control and Computer Sciences, 2011, vol. 45, no. 5, pp. 268–276. doi: 10.3103/S014641161105004X
10. Bogatyrev V.A. Fault tolerance of clusters configurations with direct connection of storage devices. Automatic Control and Computer Sciences, 2011, vol. 45, no. 6, pp. 330–337. doi: 10.3103/S0146411611060046
11.Bogatyrev S.V., Bogatyrev V.A. Kriterii optimal'nosti mnogourovnevykh otkazoustoichivykh komp'yuternykh system [Optimality criteria of multilevel failure-safe computer systems]. Scientific and Technical Journal of Information Technologies, Mechanics and Optics, 2009, no. 5 (63), pp. 92–97.
12.Bogatyrev V.A., Bogatyrev A.V. Funktsional'naya nadezhnost' sistem real'nogo vremeni [Functional reliability of real-time systems]. Scientific and Technical Journal of Information Technologies, Mechanics and Optics, 2013, no. 4 (86), pp. 150–151.
13.Muroga S., Kambayashi Y., Lai H.C., Culliney J.N. Transduction method – design of logic networks based on permissible functions. IEEE Transactions of Computers, 1989, vol. 38, no. 10, pp. 1404–1424. doi: 10.1109/12.35836
14.Lin B., Touati H.J., Newton A.R. Don’t care minimization of multi-level sequential logic networks. Proc. IEEE International Conference on Computer-Aided Design, 1990, pp. 414–417.
15.Brayton R.K., Hachtel G., McMullen C., Sangiovanni-Vincentelli A. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1985, 206 p.
16.Theobald M., Nowick S.M., Wu T. Espresso-HF: a heuristic hazard-free minimizer for two-level logic. Proceedings - Design Automation Conference. Las Vegas, USA, 1996, pp. 71–76.
17.Codd E.F. A relational model of data for large shared data banks. M.D. Computing, 1998, vol. 15, no. 3, pp. 162–166.
18.Abiteboul S., Hull R., Vianu V. Foundations of Databases. Addison-Wesley, 1995, 685 p.
19.Date C.J., Darwen H. Foundation for Future Database Systems: The Third Manifesto. 2nd ed. Addison-Wesley, 2000, 608 p.