ALGORITHM OF RATIONAL PROCESSOR ARCHITECTURE

The paper deals with an algorithm that makes it possible to decide on processor architecture for computational kernel. This architecture provides the maximum possible rate of the computational process. The algorithm is based on a sliding window method applied to bottlenecks - fragments of program code taking a maximum percentage of time for execution. The algorithm calculates a rational number of arithmetic-logic processor core computing channels depending on the type of supported operations. Calculation of the rational number for arithmetic and logical channels of processor architecture is performed on the code example that implements the algorithm for calculating the tesseral harmonics of the Earth gravitational field. Arithmetic operations of integer and real addition (subtraction), real multiplication, as well as the operations of calculating the values of logical predicates, were considered in the example. Calculation results revealed that for considered example, rational variant of processor architecture should include two arithmetic logic channels capable of performing these operations. The developed algorithm is feasible for application in solving the synthesis tasks for processor architectures and computing systems based on them. Maximum effect after using the algorithm results is achieved at the synthesis of computing systems that perform tasks on the basis of a consistent mathematical tool.

1. Trakhtengerts E.A. The effect of architecture and structure of multiprocessor computers on programming languages and translation methods. Avtomatika i Telemekhanika, 1986, no. 3, pp. 5–47.

2. Rumyantsev A.S. Metod otobrazheniya zadach na krupnogranulyarnye rekonfiguriruemye vychislitel'nye sistemy [Tasks mapping method for coarse grain reconfigurable systems]. Scientific and Technical Journal of Information Technologies, Mechanics and Optics, 2014, no. 1 (89), pp. 76–81. 

3. Bogdanov A.Yu., Perekatov V.I., Feldman V.M. Kommunikatsionnye interfeisy mezhmashinnykh svyazei vychislitel'nykh sredstv semeistva «El'brus» [Communication interfaces of Elbrus computer means untermachine liasons]. Voprosy Radioelektroniki, 2013, vol. 4, no. 3, pp. 72–83.

4. Myskin A.V., Torgashev V.A., Tsaryov I.V. Protsessory s dinamicheskoi arkhitekturoi na osnove skhem gibkoi logiki [Processors with dynamic architecture based on flexible logic devices]. Trudy SPIIRAN, 2002, vol. 1, no. 1, pp. 113–128.

5. Bacon D.F., Grahem S.L., Sharp O.J. Compiler transformations for high-perfomance computing. ACM Computing Surveys, 1994, vol. 26, no. 4, pp. 345–420. doi: 10.1145/197405.197406

6. Molka D., Hackenberg D., Schone R., Muller M.S. Memory performance and cache coherency effects on an Intel Nehalem multiprocessor system. Proc. 18th Int. Conf. on Parallel Architectures and Compilation Techniques. Dresden, Germany, 2009, pp. 261–270. doi: 10.1109/PACT.2009.22

7. Stegajlov V.V., Norman G.E. Problemy razvitiya superkomp'yuternoi otrasli v Rossii: vzglyad pol'zovatelya vysokoproizvoditel'nykh sistem [Challenges to the supercomputer development in Russia: a HPC user perspective]. Programmnye Sistemy: Teoriya i Prilozheniya, 2014, vol. 5, no. 1–1 (19), pp. 111–152.

8. Toporkov V.V. Modeli Raspredelennykh Vychislenii [Models of Distributed Computing]. Moscow, Fizmatlit Publ., 2004, 320 p.

9. Tel G. Introduction to Distributed Algorithms. 2nd ed. Cambridge University Press, 2000, 612 p.

10. Karpov V.E., Lobanov A.I. Chislennye Metody, Algoritmy i Programmy. Vvedenie v Rasparallelivanie [Numerical Methods, Algorithms and Programs. Introduction to Parallelization]. Moscow, Fizmatkniga Publ., 2014, 196 p.

11. Cheburakhin I.F. Sintez Diskretnykh Upravlyayushchikh Sistem i Matematicheskoe Modelirovanie [Synthesis of Discrete Control Systems and Mathematical Modeling]. Moscow, Fizmatlit Publ., 2004, 247 p.

12. Reznikov B.A. Metodologiya Sistemnykh Iissledovanii. Modelirovanie Slozhnykh Sistem [The Methodology of Systems Research. Modeling of Complex Systems]. Leningrad, MO USSR Publ., 1990, 522 p.

13. Roy A.E. Orbital Motion. Bristol, UK, Adam Hilger ltd, 1978.

14. Kim A.K., Perekatov V.I., Ermakov S.G. Mikroprotsessory i Vychislitel'nye Kompleksy Semeistva «El'brus» [Microprocessors and Computer Systems of the Family "Elbrus"]. St. Petersburg, Piter Publ., 2013, 272 p.

15. Gergel' V.P., Meerov I.B., Bastrakov S.I. Vvedenie v printsipy funktsionirovaniya i primeneniya sovremennykh mul'tiyadernykh arkhitektur (na primere Intel Xeon Phi) [Introduction to the principles of operation and application of modern multicore architectures, for example, Intel Xeon Phi]. Available at: http://www.intuit.ru/studies/courses/10611/1095/info (accessed 30.09.2014).

16. Rau B.R. Iterative modulo scheduling: an algorithm for software pipelining loops. Professional Engineering, 1994, vol.7, no. 21, pp. 63–74.

This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License