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Editor-in-Chief
Nikiforov
Vladimir O.
D.Sc., Prof.
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doi: 10.17586/2226-1494-2015-15-3-463-469
CENTRALIZED MAC PROTOCOL FOR HIERARCHICAL CACHING PROCESSORS
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Article in Russian
For citation: Antonov A.A., Kluchev A.O., Komar M.S., Kustarev P.V., Koucheryavy Ye.A., Moltchanov D.A., Petrov V.I., Platunov A.E. Applicability Centralized MAC protocol for hierarchical caching processors. Scientific and Technical Journal of Information Technologies, Mechanics and Optics, 2015, vol.15, no. 3, pp. 463–469.
Abstract
For citation: Antonov A.A., Kluchev A.O., Komar M.S., Kustarev P.V., Koucheryavy Ye.A., Moltchanov D.A., Petrov V.I., Platunov A.E. Applicability Centralized MAC protocol for hierarchical caching processors. Scientific and Technical Journal of Information Technologies, Mechanics and Optics, 2015, vol.15, no. 3, pp. 463–469.
Abstract
The subject of research is the architecture of modern processors with hierarchical organization of cache subsystem. Analysis of implementation possibility of wireless connectivity between cores and Level 3 cache has been carried out. In order tospecify the requirements to wireless communication channel, communication in modern general-purpose processors has been explored by an example of Intel Core i7 (Haswell). Interaction model of cache subsystem components has been developed, and on its basis interaction characteristics between them are being evaluated. Analysis of the model shows that the latency of cache line transmission via the proposed channel is about 0.26 nanoseconds, which correlates well with the latency of L1 cache (about 2 nanoseconds). Also, wireless channel satisfies the distance requirements, giving the possibility for data transmission upto 3 centimeters, as well as power requirements with consumption of 1 uW. The result of research is the developed medium access protocol for wireless connectivity between computational cores and Level 3 cache. To account for required simplicity of implementation and efficiency of operation, it is proposed to use the single frequency range for all radio interfaces and time division multiple access scheme with prescribed fields for addressing and data. The paper deals with protocol data unit structure, which is used for communication between units. Possibility of shared time counter creationis used for synchronization between units. Time division duplex with possibly dynamic non-equal time shares is used to organize uplink and downlink communications. Time division mechanism gives the possibility for the system to adapt to load irregularities between the cores through allocation of various amounts of time slots for each core.
Keywords: general-purposeprocessors, hierarchicalcache, terahertzfrequency range, wireless multiple access.
Acknowledgements. This work was carried out within Academy of Finland FiDiPro program ''Nano Communication Networks'', 2012–2016, and partially financially supported by the Government of the Russian Federation, Grant 074-U01.
References
Acknowledgements. This work was carried out within Academy of Finland FiDiPro program ''Nano Communication Networks'', 2012–2016, and partially financially supported by the Government of the Russian Federation, Grant 074-U01.
References
1. Martin C. Multicore processors: challenges, opportunities, emerging trends. Proc. Embedded World Conference 2014. Nuremberg, Germany, 2014, pp. 1–9.
2. Bjerregaard T., Mahadevan S. A survey of research and practices of network-on-chip. ACM Computing Surveys, 2006, vol. 38, no. 1, pp. 71–121.
3. Chang K., Deb S., Ganguly A., Yu X., Sah S.P., Pande P.P., Belzer B., Heo D. Performance evaluation and design trade-offs for wireless network-on-chip architectures. ACM Journal of Emerging Technologies in Computing Systems, 2012, vol. 8, no. 3, art. 23. doi: 10.1145/2287696.2287706
4. Molka D., Hackenberg D., Schone R. Main memory and cache performance of Intel Sandy Bridge and AMD Bulldozer. Proc. Workshop on Memory Systems Performance and Correctness, MSPC 2014. Edinburgh, UK, 2014, art. 4. doi: 10.1145/2618128.2618129
5. Sorin D.J., Hill M.D., Wood D.A. A primer on memory consistency and cache coherence. Synthesis Lectures on Computer Architecture, 2011, vol. 16, pp. 1–212. doi: 10.2200/S00346ED1V01Y201104CAC016
6. Bardizbanyan A., Själander M., Whalley D., Larsson-Edefors P. Reducing set-associative L1 data cache energy by early load data dependence detection (ELD3). Proc. 17th Design, Automation and Test in Europe, DATE 2014. Dresden, Germany, 2014, art. 6800296. doi: 10.7873/DATE2014.095
7. Sleiman F.M., Dreslinski R.G., Wenisch T.F. Embedded way prediction for last-level caches. Proc. IEEE 30th Int. Conf. on Computer Design. Montreal, Canada, 2012, art. 6378636, pp. 167–174. doi: 10.1109/ICCD.2012.6378636
8. Chu Y., Park J.H. Dual-access way-prediction cache for embedded systems. EURASIP Journal on Embedded Systems, 2014, vol. 2014, art. 16. doi: 10.1186/1687-3963-2014-16
9. Powell M., Agarwal A., Vijaykumar T.N., Falsafi B., Roy K. Reducing set-associative cache energy via wayprediction and selective direct-mapping. Proc. 34th Annual International Symposium on Microarchitecture ACM/IEEE. Austin, USA, 2001, pp. 54–65. doi: 10.1109/MICRO.2001.991105
10. Tota S.V., Casu M.R., Roch M.R., Rostagno L., Zamboni M. Medea: a hybrid shared-memory/messagepassing multiprocessor NoC-based architecture. Proc. Design, Automation and Test in Europe Conference and Exhibition, DATE 2010. Dresden, Germany, 2010, art. 5457237, pp. 45–50.
11. Jornet J.M., Akyildiz I.F. Channel modeling and capacity analysis for electromagnetic wireless nanonetworks in the terahertz band. IEEE Transactions on Wireless Communications, 2011, vol. 10, no. 10, pp. 3211–3221. doi: 10.1109/TWC.2011.081011.100545
12. Boronin P., Petrov V., Moltchanov D., Koucheryavy Y., Jornet J.M. Capacity and throughput analysis of nanoscale machine communication through transparency windows in the terahertz band. Nano Communication Network, 2014, vol. 5, no. 3, pp. 72–82. doi: 10.1016/j.nancom.2014.06.001
13. Komar M.S., Koucheryavy E.A., Moltchanov D.A., Petrov V.I. Raschet kharakteristik protokolov besprovodnoi svyazi dlya vzaimodeistviya mezhdu yadrami tsentral'nogo protsessora [On the wireless cacheaccess in multicore CPU over the terahertz band]. Informatsionnye Tekhnologii i Telekommunikatsii, 2014, no. 3, pp. 41–58.
14. Petrov V., Andreev S., Turlikov A., Koucheryavy Y. On IEEE 802.16m overload control for smart grid deployments. Lecture Notes in Computer Science, 2012, vol. 7469 LNCS, pp. 86–94. doi: 10.1007/978-3-642-32686-8_8
