DOI: 10.17586/2226-1494-2018-18-3-479-486


N. M. Chernetskaya, A. A. Mikhteeva, N. N. Nevirkovets, D. V. Kostygov, Y. V. Belyaev

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For citation: Chernetskaya N.M., Mikhteeva A.A., Nevirkovets N.N., Kostygov D.V., Belyaev Y.V. Verification of integrated circuit behavioral models by programmable logic. Scientific and Technical Journal of Information Technologies, Mechanics and Optics, 2018, vol. 18, no. 3, pp. 479–486 (in Russian). doi: 10.17586/2226-1494-2018-18-3-479-486


 Subject of Research. The paper considers the research of verification methods for behavioral models by the field-programmed gate array (FPGA). Applying verification with FPGA gives the possibility to identify functional errors, which are not determined at the verification phase of the traditional integrated circuits (IC) design. Method. The approach is recommendedto two-stage IC interface blocks prototyping with FPGA by means of standard IP-blocks and external devices. The addition of an extra verification phase was proposed carried out after the verification phase according to the traditional IC design path in the Cadence automated design system. Main Results. The approach was used to verify the block of the serial peripheral interface (SPI), which was included in the IC of the micromechanical accelerometer. The result of the interface block model verification showed that the first stage of prototyping with the use of standard interface IP blocks gives the possibility to reveal the existing functional errors in the device with minimal time. Without standard IP-blocks, the model of the verification device ought to be developed separately that can lead to malfunction risks of the final device. The second prototyping stage applying an external plug-in verification device makes it possible to get out of errors connected with signal propagation delays outside the IC and to avoid limitations connected with lack of necessary IP-blocks. Practical Relevance. Two-stage prototyping can be used in the design of IC interface blocks with a view to minimize the probability of errors in data transmission. Functional errors not detected during the verification phase of the traditional IC design were identified and corrected based on the results of two-stage prototyping of the SPI block model. The model designed by this approach was used to develop an IC for a micromechanical accelerometer.

Keywords: integrated circuits, FPGA, verification, prototyping, behavioral model, interface

Acknowledgements. This work was supported by the project no. 16-08-00640 of the Russian Foundation for Basic Research, Russian Federation

  1. Titovskaya T.S., Nepomnyashchii O.V., Leonova A.V., Komarov A.A. Formal verification in very large-scale integration designing. The Bulletin of KrasGAU, 2014, no. 4, pp. 87–89. (in Russian)
  2. Foster H. Conclusion: The 2016 Wilson Research Group Functional Verification Study. Available at: (accessed 5.02.18).
  3. Bukhteev A.V. Methods and tools for designing systems on a chip. ChipNews, 2003, no. 4, pp. 4–14. (in Russian)
  4. Yurlin S.V. Development of Specialized Prototypes Based on Programmable Logic for Efficient Functional Verification of Multi-Core Microprocessors. Dis. PhD Eng. Sci. Moscow, 2014. (in Russian)
  5. Wojcikowski M., Pankiewicz B. ASIC design example of complex SoC with FPGA prototyping. Przeglad Elektrotechiczny, 2013,pp. 156–158.
  6. Yurlin S.V., Bychkov I.N. FPGA prototyping for functional verification of multi-core processors. Problems of Development of Advanced Micro and Nanoelectronic Systems, 2014, no. 4, pp. 45–50. (in Russian)
  7. Myers G.J. The Art of Software Testing. Wiley, 2004.
  8. Piziali A. Functional Verification Coverage Measurement and Analysis. New York, Kluwer Academic Publishers, 2004, 216 p.
  9. Khisambeev I.Sh., Chibisov P.A. On one method of defining functional coverage metrics for microprocessor testing. Problems of Development of Advanced Micro and Nanoelectronic Systems, 2014, no. 2, pp. 63–68. (in Russian)
  10. Incisive Coverage User Guide 15.2. Cadence, 2016, 350 p.
  11. Sutherland S., Mills D.Synthesizing SystemVerilog Busting the Myth that SystemVerilog is only for Verification.SNUG Silicon Valley, 2013, 45 p.
  12. Lapin A.A. Interfaces. Selection and Implementation. Moscow, Tehnosfera Publ., 2005, 168 p. (in Russian)
  13. NIOS II Processor - Overview. Available at: (accessed 13.02.2018).
  14. Kovach N. Logical Analyzer SignalTap. Available at: (accessed 13.02.2018).
  15. Milandr 1986ВЕ1ТMicrocontroller Specification. Available at: (accessed 10.02.2018).

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