HIGH-LEVEL SYNTHESIS SYSTEM BASED ON HYBRID RECONFIGURABLE MICROARCHITECTURE  

Penskoi A.V., Platunov A.E., Kluchev A.O., Gorbachev Ya.G., Yanalov R.I.  High-level synthesis system based on hybrid reconfigurable microarchitecture. Scientific and Technical Journal of Information Technologies, Mechanics and Optics, 2019, vol. 19, no. 2,  pp. 306–313 (in Russian).

doi: 10.17586/2226-1494-2019-19-2-306-313

Subject of Research. The paper presents research of state-of-the-art methods of real-time hardware / software systems development based on FPGAs and SoCs. High-level synthesis system based on the hybrid reconfigurable NISC/TTA microarchitecture is proposed. Method. The work is based on analysis and synthesis of computer architectures and their design methods within Model-Driven Engineering, High-Level Synthesis and Hardware/Software Codesign methodologies. Main Results. Analysis of academic and commercial tools for development of hardware/software systems based on FPGAs and SoCs is performed. The key factors are determined limiting the wide introduction of high-level synthesis tools in industry. The ideology and architecture of the high-level synthesis system are developed on the basis of the original reconfigurable NISC/TTA microarchitecture. The prototype of the considered EDA system is developed. The synthesis tool and the synthesis process control interface are among the most valuable outcomes and give the possibility to explore the results of synthesis decisions made by the tool, and control the process either manually or automatically. The visualization interface of the target computational process is implemented that allows for effective representation of its multi-level organization. The end-to-end testing system is developed enabling verification of compliance between a synthesized system and its functional model. Practical Relevance. The tools implemented as part of the CAD prototype have made the synthesis process transparent and manageable for the designer and demonstrated the possibility of finding compromise design solutions in semi-automatic mode. We managed to control flexibly heuristics in the synthesizer operation, not only reducing design iterations, but also making the process convergent in principle, which is not provided by alternative technologies in many cases. NISC/TTA microarchitecture played an important role in this process. Solution of a number of test problems has shown that this design platform can be recommended for implementation of control algorithms in real-time systems and for the application in system dynamics modeling.

1. Lee E.A., Seshia S.A. Introduction to Embedded Systems: A Cyber-Physical Systems Approach. 2nd ed. MIT Press, 2017.

2. Hemsoth N., Morgan T.P. FPGA Frontiers: New Applications in Reconfigurable Computing. Next Platform Press, 2017, 182 p.

3. Hartenstein R. SE Curricula are Unqualified to Cope with the Data Avalanche. 2017. 23 p. Available at: hartenstein.de/publications/CS.pdf (accessed: 09.03.2018).

4. Pelcat M. et al. Design productivity of a high level synthesis compiler versus HDL. Proc. Int. Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS, 2016, pp. 140–147. doi: 10.1109/samos.2016.7818341

5. Harris D., Harris S. Digital Design and Computer Architecture. 2nd ed. Morgan Kaufman, 2012.

6. Platunov A.E. Theoretical and Methodological Bases of HighLevel Design of Embedded Computing Systems. St. Petersburg, ITMO University Publ., 2010, 477 p. (in Russian)

7. Nane R. et al. A survey and evaluation of FPGA high-level synthesis tools. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, vol. 35, no. 10, pp. 1591–1604. doi: 10.1109/tcad.2015.2513673

8. Fingeroff M. High-Level Synthesis Blue Book. Xlibris, 2010, 332 p.

9. Bailey B. ESL Flow is Dead. Semiconductor Engineering, 2016. Available at: semiengineering.com/esl-flow-is-dead (accessed: 09.03.2018).

10. Teich J., Henkel J., Herkersdorf A. et al. Invasive computing: an overview. Multiprocessor System-on-Chip, 2011, pp. 241–268. doi: 10.1007/978-1-4419-6460-1_11

11. Dmitrochenko L.A., Sachkov G.P. Functional algorithms and attitude determination error equations for strap-down inertial navigation systems. Trudy MAI, 2015, no. 80, 24 p. (in Russian)

12. Zaytsev D.Y., Neretin E.S., Ramzaev A.M. Universal avionics modular controller architecture development. Trudy MAI, 2016, no. 85, 29 p. (in Russian)

13. Henkel J., Parameswaran S. Designing Embedded Processors: A Low Power Perspective. Springer, 2007, 550 p. doi: 10.1007/978-1-4020-5869-1

14. Corporaal H., Arnold M. Using transport triggered architectures for embedded processor design. Integrated Computer-Aided Engineering, 1998, vol. 5, no. 1, pp. 19–38. doi: 10.3233/ica1998-5103

15. Kovyazin R.R., Postnikov N.P. Problem-oriented processors design. Scientific and Technical Journal of Information Technologies, Mechanics and Optics, 2010, no. 6, pp. 81–85. (in Russian)

16. Golubok A.O., Platunov A.E., Sapozhnikov I.D. Control system for a scanning-probe microscope. Nauchnoe Priborostroenie, 2003, vol. 13, no. 3, pp. 25–31. (in Russian)

17. Teich J. Hardware/Software codesign: the past, the present, and predicting the future. Proceedings of the IEEE, 2012, vol. 100, pp. 1411–1430. doi: 10.1109/JPROC.2011.2182009

18. Kluchev A., Platunov A., Penskoi A. HLD - methodology in embedded systems design with a multilevel reconfiguration. Proc. 3rd Mediterranean Conference on Embedded Computing, MECO-2014. Budva, Montenegro, 2014, pp. 36–39. doi: 10.1109/meco.2014.6862729

19. Penskoi A. V. Architectural specification of embedded systems with multi-level configuration. Izvestiya Vysshikh Uchebnykh Zavedeniy. Priborostroenie, 2015, vol. 58, no. 7, pp. 527–532. (in Russian)

20. Penskoi A., Gaiosh A., Platunov A., Kluchev A. Specialised computational platform for system dynamics. Proc. 18th International Multidisciplinary Scientific GeoConference, 2018, vol. 18, no. 2.1, pp. 709–716. doi: 10.5593/sgem2018/2.1/s07.090

21. Hughes J. Generalizing monads to arrows. Science of Computer Programming, 2000, vol. 37, no. 1-3, pp. 67–111. doi: 10.1016/s0167-6423(99)00023-4

22. Perl I., Mulyukin A., Kossovich T. Continuous execution of system dynamics models on input data stream. Proc. 20th Conference of Open Innovations Association, FRUCT, 2017, pp. 371–376. doi: 10.23919/fruct.2017.8071336

This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License