PERFORMANCE EVALUATION OF SD-CARDS BY "SYSTEM-ON-CHIP" TECHNOLOGY

Subject matter. We propose the hardware and software block for performing write or read operation and testing the performance of different SD-cards using the technology of "system-on-chip" in integrated environment by Altera. This task is relevant for the design of high-performance parallel systems on a chip, where the lower limit for writing speed (and/or reading) is critical and significant. Method. The proposed approach is based on three items. First, schemes are used with programmable logic to create a compact hardware and software unit as part of video system on chip. Secondly, reprogrammable structures are applied that support serial and parallel modes of exchange. Thirdly, the increment of data bus width is possible, via the serial transfer and the parallel connection of multiple units simultaneously. Main Results. The analysis of test results of different memory cards has shown that the speed of writing and reading for all cards differs from the declared one by manufacturer, and the error rate of writing (and reading) of data is 30...50% (for reading ~30%). A maximum download speed of memory cards is possible by increasing the number of cascade-connected blocks. The results show that the simplest implementation of this hardware-software unit requires resources of the order of 2000-2500 elementary logic cells. Each cell implements the logical operation "AND-OR with memory", while the resource ЕР3С25F256C8 of the popular chip family Cyclone III consists of 5976 (26%) of these cells with the chip price equal to $5-10 apiece. Practical Relevance. The authors believe that the proposed hardware-software unit can be regarded as the cheapest specialized component in the ECB domestic microelectronics industry to create video information in real time systems.
 

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