DOI: 10.17586/2226-1494-2015-15-6-1088-1097


PERFORMANCE EVALUATION OF SD-CARDS BY "SYSTEM-ON-CHIP" TECHNOLOGY

E. V. Kostikova, G. A. Gavrilov, Y. I. Mukalo, Y. V. Alekseenko, S. S. Fahmi


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Article in Russian

For citation: Kostikova E.V., Gavrilov I.A., Mukalo Yu.I., Alekseenko Ya.V., Fahmi Sh.S. Performance evaluation of SD – cards by "system-on-chip" technology. Scientific and Technical Journal of Information Technologies, Mechanics and Optics, 2015, vol. 15, no. 6, pp. 1088–1097.

Abstract

Subject matter. We propose the hardware and software block for performing write or read operation and testing the performance of different SD-cards using the technology of "system-on-chip" in integrated environment by Altera. This task is relevant for the design of high-performance parallel systems on a chip, where the lower limit for writing speed (and/or reading) is critical and significant. Method. The proposed approach is based on three items. First, schemes are used with programmable logic to create a compact hardware and software unit as part of video system on chip. Secondly, reprogrammable structures are applied that support serial and parallel modes of exchange. Thirdly, the increment of data bus width is possible, via the serial transfer and the parallel connection of multiple units simultaneously. Main Results. The analysis of test results of different memory cards has shown that the speed of writing and reading for all cards differs from the declared one by manufacturer, and the error rate of writing (and reading) of data is 30...50% (for reading ~30%). A maximum download speed of memory cards is possible by increasing the number of cascade-connected blocks. The results show that the simplest implementation of this hardware-software unit requires resources of the order of 2000-2500 elementary logic cells. Each cell implements the logical operation "AND-OR with memory", while the resource ЕР3С25F256C8 of the popular chip family Cyclone III consists of 5976 (26%) of these cells with the chip price equal to $5-10 apiece. Practical Relevance. The authors believe that the proposed hardware-software unit can be regarded as the cheapest specialized component in the ECB domestic microelectronics industry to create video information in real time systems.
 


Keywords: SD card, performance, writing and reading speed, FPGA, systems on chip, concurrency

References

1. Mel'nichenko A. Tekhnologiya Miniatyurizatsii REA [Radio-Electronics Miniaturization Technology]. Feniks Publ., 2009, 486 p.
2. Nguyen K.D., Sun Z., Thiagarajan P.S., Weng-Fai Wong. Model-driven SoC design via executable UML to SystemC. Proc. 25th IEEE Real-Time Systems Symposium, RTSS'04. Lisbon, Portugal, 2004.
3. Nemudrov V., Martin G. Sistemy na Kristalle. Proektirovanie i Razvitie [Systems on a Chip. Design and Development]. Moscow, Tekhnosfera Publ., 2004, 216 p.
4. Inside Solid State Drives (SSDs). Eds. R. Micheloni, A. Marelli, K. Eshghi. Springer, 2013, 382 p.
5. Zhu Q., Pileggi L., Franchettis F. Cost-effective smart memory implementation for parallel backprojection in computed tomography. Proc. 20th IFIP/IEEE Int. Conf. on Very Large Scale Integration. Santa Cruz, USA, 2012, pp. 111–116. doi: 10.1109/VLSI-SoC.2012.6379015
6. Park C., Talawar P., Won D., Jung M., Im J., Kim S., Choi Y. A high performance controller for NAND flash-based solid state disk (NSSD). Proc. 21th IEEE Non-Volatile Semiconductor Memory Workshop, NVSMW 2006. Monteray, USA, 2006, pp. 17–20. doi: 10.1109/.2006.1629477
7. Agrafiotis D., Canagarajah N., Bull D.R., Kyle J., Seers H., Dye M. A perceptually optimised video coding system for sign language communication at low bit rates. Signal Processing: Image Communication, 2006, vol. 21, no. 7, pp. 531–549. doi: 10.1016/j.image.2006.02.003
8. Nakazono K., Nagashima Y., Ichikawa A. Digital encoding applied to sign language video. IEICE Transactions on Information and Systems, 2006, vol. E89-D, no. 6, pp. 1893–1900. doi: 10.1093/ietisy/e89-d.6.1893
9. Lanne A.A. Tsifrovoi Protsessor Obrabotki Signalov TMS320C10 i ego Primeneniya [The Digital Signal Processor TMS320C10 and its Application]. Leningrad, VAS Publ., 1990, 296 p.
10. Protsessory Tsifrovoi Obrabotki Signalov Kompanii Texas Instruments Inc [Digital Signal Processors of Texas Instruments Inc]. Moscow, SKAN Publ., 1999.
11. Zubakin I.A., Tsytsulin A.K. Modelirovanie vliyaniya ogranicheniya slozhnosti kodera na kachestvo kodirovaniya izobrazhenii s preobrazovaniem [Modeling of the limiting effect of encoder complexity on the quality of image coding with transformation]. Voprosy Radioelektroniki. Ser. Tekhnika Televideniya, 2006, no. 2, pp. 32–40.
12. Vanam R., Riskin E.A., Ladner R.E. H.264/MPEG-4 AVC encoder parameter selection algorithms for complexity distortion tradeoff. Proc. Data Compression Conference, DCC 2009. Snowbird, USA, 2009, art. 4976481, pp. 372–381.
13. Valentim J., Nunes P., Pereia F. An alternative complexity model for the MPEG-4 video verifier mechanism. Proc. IEEE Int. Conf. on Image Processing, ICIP2001. Thessaloniki, Greece, 2001, vol. 1, pp. 461–464.
14. Tsytsulin A.K., Fahmi Sh.S., Kolesnilov E.I., Ochkur S.V. Functional interchange of transmission rate and complexity of the coder continuous signal. Informatsionnye Tekhnologii, 2011, no. 4, pp. 71–77. (In Russian)
15. Fahmi Sh.S., Labetzky A.V. Ip-core for read/write videodata to/from sd card. Voprosy Radioelektroniki. Ser. Tekhnika Televideniya, 2014, no. 1, pp. 107–115. (In Russian)
16. Zubakin I.A., Fahmi Sh.S. Adaptive algorithm of coding and decoding of the video information on the basis of three-demensional discrete cosine transform. Izv. vuzov Rossii. Radioelektronika, 2010, no. 1, pp. 49–54. (In Russian)
17. van Schaar M., Andreopoulos Y. Rate-distortion-complexity modeling for network and receiver aware adaptation. IEEE Trans. on Multimedia, 2005, vol. 7, no. 3, pp. 471–479. doi: 10.1109/TMM.2005.846790
18. Westwater R., Furht B. Real-Time Video Compression. Techniques and Algorithms. Kluwer, 1997, 172 p.
19. Marpe D., Schwarz H., Wiegand T. Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard. IEEE Trans. on Circuits and Systems for Video Technology, 2013, vol. 13, no. 7, pp. 620–636. doi: 10.1109/TCSVT.2003.815173
 



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