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Editor-in-Chief
Nikiforov
Vladimir O.
D.Sc., Prof.
Partners
doi: 10.17586/2226-1494-2019-19-3-523-530
PROCESS-ORIENTED SYNTHESIS OF SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS FOR INTEGRATED CIRCUITS
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Abstract
Mikhteeva A.A., Kolesov N.V. Process-oriented synthesis of successive approximation analog-to-digital converters for integrated circuits. Scientific and Technical Journal of Information Technologies, Mechanics and Optics, 2019, vol. 19, no. 3, pp. 523–530 (in Russian). doi: 10.17586/2226-1494-2019-19-3-523-530
Abstract
Subject of Research. High-resolution successive approximation analog-to-digital converters include a digital-to-analog converter with multiple capacitor arrays and have significant nonlinearity. Existing methods for nonlinearity reducing are aimed primarilyat nonlinearity lowering that arises in the digital-to-analog converter, which is a part of successive approximation analog-to- digital converter. These methods are not complex and are aimed only at reducing the impact of one or several factors that cause the nonlinearity of the digital-to-analog converter. In addition, the known approaches are applied only at the stage of topology development, that leads to significant time costs in the case of redesign when it is impossible to achieve the required accuracy of the analog-to-digital converter. Based on the above, we can assert the relevance of the development of process-oriented synthesis method for analog-to-digital converters reducing the transformation nonlinearity by taking into account the manufacturing technology at the early design stages. Method. A method of process-oriented synthesis for analog-to-digital converters is proposed providing analog-to-digital converter nonlinearity reducing. Main Results. As compared with the known methods, the method takes into account the peculiarities of the technological process at the early stage of device design. The method was used to design 18-bit analog-to-digital converter on 350 nm CMOS technology. Practical Relevance. The proposed method can be used for high-resolution analog-to-digital converter design on different CMOS technologies.
Keywords: microelectronics, integrated circuit, analog-to-digital converter, synthesis, parasitic parameters
Acknowledgements. This work was supported by the project No. 16-08-00640 of the Russian Foundation for Basic Research, Russian Federation.
References
Acknowledgements. This work was supported by the project No. 16-08-00640 of the Russian Foundation for Basic Research, Russian Federation.
References
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2. Hastings A. The Art of Analog Layout. 2nd ed. Prentice Hall, 2006, 672 p.
3. Maloberti F. Analog Design for CMOS VLSI Systems. Kluwer Academic Publ., 2003, 374 p. doi: 10.1007/b100812
4. Lin M.P.H., He Y.T., Hsiao V.W.H., Chang R.G., Lee S.Y. Common-centroid capacitor layout generation considering device matching and parasitic minimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, vol. 32, no. 7, pp. 991–1002. doi: 10.1109/ tcad.2012.2226457
5. Hsiao W.H., He Y.T., Lin M.P., Chang R.G., Lee S.Y. Automatic common-centroid layout generation for binary-weight capacitors in charge-scaling DAC. Proc. Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. Seville, Spain, 2012, pp. 173–176. doi: 10.1109/smacd.2012.6339445
6. Lin C.W., Lin J.M., Chiu Y.C., Huang C.P., Chang S.J. Mismatch-aware common-centroid placement for arbitrary- ratio capacitor arrays considering dummy capacitors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012, vol. 31, no. 12, pp. 1789–1802. doi: 10.1109/tcad.2012.2204993
7. Zhu Y., Chio U.F., Wei H.G., Sin S.W., Seng-Pan U., Martins
R.P. Linearity analysis on a series-split capacitor array for high-speed SAR ADCs. Proc. 51st Midwest Symposium on Circuits and Systems. Knoxville, USA, 2008, pp. 922–925. doi: 10.1109/mwscas.2008.4616951
8. Zhang Y., Zhao Y., Dai P. Study of split capacitor DAC mismatch and calibration in SAR ADC. Journal of Circuits System and Computers, 2015, vol. 26, no. 1. doi: 10.1142/s0218126617500037
9. McNeill J.A. et al. All-digital background calibration of successive approximation ADC using split ADC architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 2011, vol. 58, no. 10, pp. 2355–2365. doi: 10.1109/tcsi.2011.2123590
10. Rikan B.S., Abbasizadeh H., Do S.-H., Lee D.-S., Lee K.Y. Digital error correction for a 10-bit straightforward SAR ADC. IEEE Transactions on Smart Processing and Computing, 2015, vol. 4, no. 1, pp. 51–58. doi: 10.5573/ieiespc.2015.4.1.051
11. Ogawa T., Kobayashi H., Hotta M., Takahashi Y., Hao S., Nobukazu T. SAR ADC algorithm with redundancy. Proc. IEEE Asia Pacific Conference on Circuits and Systems. Macao, 2008, pp. 268–271. doi: 10.1109/apccas.2008.4746011
12. Chang A.H., Lee H.S., Boning D. A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration. Proc. of the ESSCIRC. Bucharest, 2013, pp. 109–112. doi: 10.1109/esscirc.2013.6649084
13. Zhao Y., Nan J., Dai P., Yang M. Digital self-calibration technique based on 14-bit SAR ADC. Transactions of Tianjin University, 2013, vol. 19, no. 6, pp. 454–458. doi: 10.1007/s12209-013-2015-7
14. Arian M., Saberi S., Hosseini-Khayat R., Lotfi Y., Leblebici A. 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC. Analog Integrated Circuits and Signal Processing, 2012, vol. 71, no. 3, pp. 583–589. doi: 10.1007/s10470-011-9812-5
15. Chen Y. Split capacitor DAC mismatch calibration in successive approximation ADC. IEEE Custom Integrated Circuits Conference. San Jose, 2009, pp. 279–282. doi: 10.1109/cicc.2009.5280859
16. Ling D. A digital background calibration technique for successive approximation register analog-to-digital converter. Journal of Computer and Communications, 2013, vol. 1, no. 6, pp. 30–36. doi: 10.4236/jcc.2013.16006
17. Chang A.H. Low-power high-performance SAR ADC with redundancy and digital background calibration, PhD Thesis. Massachusetts Institute of Technology, 2013, 199 p. Available at: http://dspace.mit.edu/handle/1721.1/82177 (accessed 01.05.2019).
18. Jin L., Chen D., Geiger R. A digital self-calibration algorithm for ADCs based on histogram test using low-linearity input signals. IEEE International Symposium on Circuits and Systems. Kobe, 2005, pp. 1378–1381. doi: 10.1109/iscas.2005.1464853
19. Andryakov Yu.A., Anikina A.A., Belyaev Ya.V. Architecture selection and parameter calculation of a capacitive digital-to- analog converter for a micromechanical accelerometer. Nauchno- Tekhnicheskie Vedomosti SPbGPU, 2016, no. 4, pp. 19–28. (in Russian)
20. Mikhteeva A.A., Lemko I.V. Synthesis method of digital-to- analog converter schematic models for integrated circuits. Scientific and Technical Journal of Information Technologies, Mechanics and Optics, 2018, vol. 18, no. 2, pp. 331–338 (in Russian). doi: 10.17586/2226-1494-2018-18-2-331-338
